This invention relates to programmable logic devices, and more particularly to circuitry for improving the multiplexing capabilities of programmable logic devices.
Programmable logic devices are well known as shown, for example, by Cliff et al. U.S. Pat. No. 5,689,195, Cliff et al. U.S. patent application Ser. No. 08/909,126, Cliff et al. U.S. patent application Ser. No. 08/963,049, Reddy et al. U.S. patent application Ser. No. 08/977,793, and McClintock et al. U.S. patent application Ser. No. 08/999,016, all of which are hereby incorporated by reference herein. Such devices typically include large numbers of relatively small logic modules, each of which is programmable to perform any of several relatively elementary logic functions on input signals applied to the logic module in order to produce one or more logic module output signals. A network of programmable interconnection conductors and other interconnection resources is provided on the device for conveying signals to, from, and/or between the logic modules so that very complex logic functions can be performed by concatenating multiple logic modules in various ways.
Logic modules (also sometimes called subregions) may be grouped together on a programmable logic device in a plurality of so-called regions of programmable logic. Regions may in turn be similarly grouped together on a programmable logic device in a plurality of so-called super-regions of programmable logic. Interconnection resources may be associated with each level in this hierarchy of subregions, regions, and super-regions, and additional interconnection resources may be provided for communicating between the hierarchical levels. For example, inter-subregion interconnection conductors may be provided for conveying signals between the subregions in each region. In addition, inter-region interconnection conductors may be provided for conveying signals between the regions in each super-region. And inter-super-region interconnection conductors may be provided for conveying signals between the super-regions.
The circuitry of known programmable logic devices performs logic very well, and it can also perform some multiplexing operations. (By "multiplexing" is meant the dynamic selection of any one of two or more multiplexer input signals to be the multiplexer output signal. In other words, at different times during operation of the device, different ones of the multiplexer input signals can be selected as the multiplexer output signal.) However, known programmable logic devices tend not to perform multiplexing especially efficiently. For example, known logic modules which include a four-input look-up table may only be able to perform a single two-to-one multiplexing operation. Two of the inputs to the look-up table are used as the multiplexer input signals, a third input to the look-up table is used as a multiplexer selection control signal, and the fourth input to the look-up table may be wasted. Not only is this relatively inefficient use of a logic module, but in addition large numbers of logic modules must be used to perform wide fan-in multiplexing, and these modules must be connected in series (at least to some extent), which inevitably slows down multiplexing operations. Also, the typical absence of dynamic multiplexing capability in the interconnection resources of programmable logic devices means that if multiplexing is desired at any level in a hierarchical structure, the signals to be multiplexed must first be applied to the logic module level where multiplexing can be done and then returned to the hierarchical level requiring the multiplexing (assuming that this hierarchical level is not the logic module level). This can necessitate substantial amounts of inter-level communication, which can be wasteful of resources on the device and which may again slow down multiplexing operations.
In view of the foregoing, it is an object of this invention to provide programmable logic devices with improved multiplexing capabilities.
It is a more particular object of this invention to provide programmable logic devices with multiplexing capabilities in the interconnection resources of those devices.